1. Field of the Invention
The present invention relates, in general, to the transmission of binary data between digital devices, and, more particularly, to enabling existing and newly designed serial-in-parallel out (SIPO) shift registers to perform their own bit count, report the receipt of valid transmissions of various expected lengths, and report the receipt of certain invalid transmissions.
2. Description of Related Art
Digital data is often transmitted serially between digital devices via a combination of transmitting Parallel-In-Serial-Out (PISO) and receiving SIPO shift registers. It is prudent for a receiving SIPO shift register to report and verify that it has received a valid transmission of some expected number of bits—i.e., a packet or message of a particular, predetermined length. To this end, SIPO shift registers often operate in conjunction with an associated binary counter uniquely designed to report receipt of the expected number of bits of a message transmission. In general, there are several difficulties and shortcomings in current approaches to this requirement. First, there is the need to design a unique counter for each application, dependent on the expected length of transmissions. There is also the need to provide the flip-flops and one or more gates needed to equip the counter, and to report and verify receipt of a transmission of the expected number of bits. This, in turn, requires supplying additional surface area on a printed circuit card in order to mount the counter components. Such additional components increase the power used and heat generated the overall circuitry. Moreover, these additional components increase the amount of printed traces, or circuit wiring, required on a printed circuit card on which all of these components are mounted.
For certain applications, it may be desirable to send transmissions of varying numbers of expected bits. This raises additional problems. First, this can require adding a second SIPO shift register for the second potential message length, having the same issues described above.
Accordingly, it is an object of the present invention to supply a single design requiring few components, applicable to SIPO shift registers of any number of bits, that eliminates the need to design a unique associated bit counter for each different expected number of bits transmitted.
It is another object of the present invention to reduce to a single integrated circuit, or to eliminate the external components required to perform, the bit count and other functions and to enable a SIPO shift register to receive transmissions of more than one expected length.
It is yet another object of the present invention to reduce the required area of a printed circuit card required to mount the external components associated with a SIPO shift register.
It is still another object of the present invention to reduce the amount of power used and heat generated, by reducing the number of digital logic components required to perform the counting and other functions commonly associated with a SIPO shift register.
It is a further object of the present invention to reduce the amount of printed wiring on a printed circuit card incorporating one or more SIPO shift registers.
It is an additional object of the present invention to eliminate or reduce the need for multiple SIPO shift registers in applications having digital message transmissions of more than one predetermined bit length.
These and other objects and features of the present invention will become apparent in view of the present specification, drawings and claims.